Merge commit 'legko/master^^^^' into metabank

Conflicts:
	driver-bitfury.c
	libbitfury.c
	spidevc.c

driver-bitfury.c

@@ -205,7 +205,7 @@ int64_t bitfury_scanHash(struct thr_info *thr)
 			gh[bitfury->slot][chip & 0x07] = ghash;
 			snprintf(stat_lines[bitfury->slot] + len, 256 - len, "%.1f-%3.0f ", ghash, bitfury->mhz);
 
-			if(sds->short_out_t && ghash < 1.0) {
+			if(sds->short_out_t && ghash < 0.5) {
 				applog(LOG_WARNING, "Chip_id %d FREQ CHANGE", chip);
 				send_freq(bitfury->spi, bitfury->slot, bitfury->fasync, bitfury->osc6_bits - 1);
 				cgsleep_ms(1);

driver-metabank.c

@@ -64,6 +64,9 @@ struct bitfury_device **metabank_detect_chips(int *out_count) {
 	devicelist = malloc(max_devices * sizeof(*devicelist));
 	dummy_cgpu.device_data = &dummy_bitfury;
 	
+	for (i = 0; i < 32; i++) {
+		slot_on[i] = 0;
+	}
 	clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &t1);
 	for (i = 0; i < 32; i++) {
 		int slot_detected = tm_i2c_detect(i) != -1;

libbitfury.c

@@ -519,7 +519,7 @@ void libbitfury_sendHashData1(int chip_id, struct bitfury_device *d, struct thr_
 					cycles = 0x00400000 - d->ocounter1 + d->counter1; // + 0x003FFFFF;
 					ccase = 1;
 				} else {
-					cycles = d->counter1 - d->ocounter1;
+					cycles = d->counter1 > d->ocounter1 ? d->counter1 - d->ocounter1 : 0x00400000 - d->ocounter1 + d->counter1;
 					ccase = 2;
 				}
 			}
@@ -528,8 +528,9 @@ void libbitfury_sendHashData1(int chip_id, struct bitfury_device *d, struct thr_
 			ns = (double)period / (double)(cycles);
 			mhz = 1.0 / ns * 65.0 * 1000.0;
 
-			if (d->counter1 > 0 && d->counter1 < 0x001FFFFF)
+			if (d->counter1 > 0 && d->counter1 < 0x001FFFFF) {
 				applog(LOG_DEBUG, "AAA chip_id %2d: %llu ms, req1_cycles: %08u,  counter1: %08d, ocounter1: %08d, counter2: %08d, cycles: %08d, ns: %.2f, mhz: %.2f ", chip_id, period / 1000000ULL, req1_cycles, d->counter1, d->ocounter1, d->counter2, cycles, ns, mhz);
+			}
 			if (ns > 2000.0 || ns < 20) {
 				applog(LOG_DEBUG, "AAA %d!Stupid ns chip_id %2d: %llu ms, req1_cycles: %08u,  counter1: %08d, ocounter1: %08d, counter2: %08d, cycles: %08d, ns: %.2f, mhz: %.2f ", ccase, chip_id, period / 1000000ULL, req1_cycles, d->counter1, d->ocounter1, d->counter2, cycles, ns, mhz);
 				ns = 200.0;

spidevc.c

@@ -90,14 +90,14 @@ void spi_init(void)
 
 // Bit-banging reset, to reset more chips in chain - toggle for longer period... Each 3 reset cycles reset first chip in chain
 static
-void spi_reset(void)
+int spi_reset(int a)
 {
 	int i,j;
-	int a = 1234, len = 2;
+	int len = 8;
 	INP_GPIO(10); OUT_GPIO(10);
 	INP_GPIO(11); OUT_GPIO(11);
 	GPIO_SET = 1 << 11; // Set SCK
-	for (i = 0; i < 16; i++) { // On standard settings this unoptimized code produces 1 Mhz freq.
+	for (i = 0; i < 32; i++) { // On standard settings this unoptimized code produces 1 Mhz freq.
 		GPIO_SET = 1 << 10;
 		for (j = 0; j < len; j++) {
 			a *= a;
@@ -115,6 +115,8 @@ void spi_reset(void)
 	SET_GPIO_ALT(11,0);
 	INP_GPIO(9);
 	SET_GPIO_ALT(9,0);
+
+	return a;
 }
 
 #define BAILOUT(s)  do{  \
@@ -135,7 +137,7 @@ bool sys_spi_txrx(struct spi_port *port)
 	memset(&tr,0,sizeof(tr));
 	mode = 0; bits = 8; speed = 2000000;
 
-	spi_reset();
+	spi_reset(1234);
 	fd = open("/dev/spidev0.0", O_RDWR);
 	if (fd < 0) {
 		perror("Unable to open SPI device");
@@ -183,7 +185,7 @@ bool sys_spi_txrx(struct spi_port *port)
         }
 
 	close(fd);
-	spi_reset();
+	spi_reset(4321);
 
 	return true;
 }