cpu: Avoid relocations for x86_64 assembly that interfere with building BFGMiner as a PIE

x86_64/sha256_sse4_amd64.asm

@@ -24,6 +24,7 @@ BITS 64
 %define init rdx
 %define temp rcx
 %endif
+%define rel_g_4sha256_k r10
 
 ; 0 = (1024 - 256) (mod (LAB_CALC_UNROLL*LAB_CALC_PARA*16))
 %define LAB_CALC_PARA	2
@@ -49,6 +50,8 @@ CalcSha256_x64_sse4:
 	movdqa	[rsp + 16*5], xmm11
 %endif
 
+	lea	rel_g_4sha256_k, [g_4sha256_k wrt rip]
+
 LAB_NEXT_NONCE:
 
 	mov	temp, 64*4					; 256 - temp is # of SHA-2 rounds
@@ -166,7 +169,7 @@ LAB_LOOP:
 
 %macro	lab_loop_blk 0
 	movntdqa	xmm6, [data+rax*4]
-	paddd	xmm6, g_4sha256_k[rax*4]
+	paddd	xmm6, [rel_g_4sha256_k+rax*4]
 	add	rax, 4
 
 	paddd	xmm6, xmm10	; +h

x86_64/sha256_xmm_amd64.asm

@@ -25,6 +25,7 @@ BITS 64
 %define data  rdx
 %define init  rcx
 %endif
+%define rel_sha256_consts_m128i  r10
 
 ; 0 = (1024 - 256) (mod (LAB_CALC_UNROLL*LAB_CALC_PARA*16))
 %define SHA_CALC_W_PARA         2
@@ -65,11 +66,7 @@ global sha256_sse2_64_new
     pand      sr3, rE                           ; sr3 = rE & rF
     movdqa    rG, rF                            ; rG  = rF
 
-%ifidn __YASM_OBJFMT__, macho64
-    paddd     sr1, [rcx+rax]
-%else
-    paddd     sr1, sha256_consts_m128i[rax]     ; T1  =                    sha256_consts_m128i[i] + w;
-%endif
+    paddd     sr1, [rel_sha256_consts_m128i+rax] ; T1  =                    sha256_consts_m128i[i] + w;
     pxor      sr2, sr3                          ; sr2 = (rE & rF) ^ (~rE & rG) = Ch (e, f, g)
 
     movdqa    rF, rE                            ; rF  = rE
@@ -257,9 +254,7 @@ sha256_sse2_64_new:
     pshufd    rH, rE, 0xFF          ; rH == H
     pshufd    rE, rE, 0             ; rE == E
 
-%ifidn __YASM_OBJFMT__, macho64
-    lea       rcx, [sha256_consts_m128i wrt rip]
-%endif
+    lea       rel_sha256_consts_m128i, [sha256_consts_m128i wrt rip]
 
 %%SHAROUND_LOOP:
 %assign i 0