cairnsmore: Automatically "downgrade" default FPGA-per-device to 1 for dynclock devices

driver-cairnsmore.c

@@ -147,6 +147,12 @@ static bool cairnsmore_init(struct thr_info *thr)
 		       cm1->api->name, cm1->device_id,
 		       CAIRNSMORE1_DEFAULT_CLOCK, CAIRNSMORE1_MINIMUM_CLOCK, CAIRNSMORE1_MAXIMUM_CLOCK
 		);
+		// The dynamic-clocking firmware connects each FPGA as its own device
+		if (!(info->user_set & 1)) {
+			info->work_division = 1;
+			if (!(info->user_set & 2))
+				info->fpga_count = 1;
+		}
 	} else {
 		applog(LOG_WARNING, "%s %u: Frequency scaling not supported",
 			cm1->api->name, cm1->device_id

driver-icarus.c

@@ -468,6 +468,7 @@ static void get_options(int this_option_offset, struct ICARUS_INFO *info)
 				*(colon2++) = '\0';
 
 			if (*colon) {
+				info->user_set |= 1;
 				tmp = atoi(colon);
 				if (tmp == 1 || tmp == 2 || tmp == 4 || tmp == 8) {
 					*work_division = tmp;
@@ -484,6 +485,7 @@ static void get_options(int this_option_offset, struct ICARUS_INFO *info)
 					*(colon++) = '\0';
 
 			  if (*colon2) {
+				info->user_set |= 2;
 				tmp = atoi(colon2);
 				if (tmp > 0 && tmp <= *work_division)
 					*fpga_count = tmp;

icarus-common.h

@@ -70,6 +70,7 @@ struct ICARUS_INFO {
 	int fpga_count;
 	uint32_t nonce_mask;
 	bool quirk_reopen;
+	uint8_t user_set;
 
 	dclk_change_clock_func_t dclk_change_clock_func;
 	struct dclk_data dclk;