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@@ -116,6 +116,7 @@ x6500_fpga_upload_bitstream(struct cgpu_info *x6500, struct ft232r_device_handle
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applog(LOG_WARNING, "%s %u: Programming %s...",
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applog(LOG_WARNING, "%s %u: Programming %s...",
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x6500->api->name, x6500->device_id, x6500->device_path);
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x6500->api->name, x6500->device_id, x6500->device_path);
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+ // "Magic" jtag_port configured to access both FPGAs concurrently
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uint8_t dummyx;
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uint8_t dummyx;
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struct jtag_port jpt = {
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struct jtag_port jpt = {
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.ftdi = ftdi,
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.ftdi = ftdi,
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@@ -146,6 +147,8 @@ x6500_fpga_upload_bitstream(struct cgpu_info *x6500, struct ft232r_device_handle
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jtag_swrite(jp, JTAG_REG_DR, buf, 256);
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jtag_swrite(jp, JTAG_REG_DR, buf, 256);
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len -= 32;
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len -= 32;
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+ // Put ft232r chip in asynchronous bitbang mode so we don't need to read back tdo
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+ // This takes upload time down from about an hour to about 3 minutes
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if (!ft232r_set_bitmode(ftdi, 0xee, 1))
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if (!ft232r_set_bitmode(ftdi, 0xee, 1))
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return false;
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return false;
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if (!ft232r_purge_buffers(ftdi, FTDI_PURGE_BOTH))
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if (!ft232r_purge_buffers(ftdi, FTDI_PURGE_BOTH))
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@@ -168,6 +171,7 @@ x6500_fpga_upload_bitstream(struct cgpu_info *x6500, struct ft232r_device_handle
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len -= buflen;
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len -= buflen;
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}
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}
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+ // Switch back to synchronous bitbang mode
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if (!ft232r_set_bitmode(ftdi, 0xee, 4))
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if (!ft232r_set_bitmode(ftdi, 0xee, 4))
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return false;
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return false;
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if (!ft232r_purge_buffers(ftdi, FTDI_PURGE_BOTH))
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if (!ft232r_purge_buffers(ftdi, FTDI_PURGE_BOTH))
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