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@@ -85,6 +85,7 @@ struct knc_titan_info {
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struct cgpu_info *cgpu;
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int cores;
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struct knc_titan_die dies[KNC_TITAN_MAX_ASICS][KNC_TITAN_DIES_PER_ASIC];
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+ bool asic_served_by_fpga[KNC_TITAN_MAX_ASICS];
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struct work *workqueue;
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int workqueue_size;
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@@ -360,6 +361,7 @@ static bool knc_titan_init(struct thr_info * const thr)
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}
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knc->cores = total_cores;
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+ knc->asic_served_by_fpga[asic] = true;
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}
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cgpu_set_defaults(cgpu);
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@@ -369,6 +371,9 @@ static bool knc_titan_init(struct thr_info * const thr)
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knc = cgpu->device_data;
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for (asic = 0; asic < KNC_TITAN_MAX_ASICS; ++asic) {
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+ knc_titan_setup_spi("ASIC", knc->ctx, asic, KNC_TITAN_FPGA_SPI_DIVIDER,
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+ KNC_TITAN_FPGA_SPI_PRECLK, KNC_TITAN_FPGA_SPI_DECLK,
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+ KNC_TITAN_FPGA_SPI_SSLOWMIN);
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for (die = 0; die < KNC_TITAN_DIES_PER_ASIC; ++die) {
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configure_one_die(knc, asic, die);
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knc->dies[asic][die].next_slot = KNC_TITAN_MIN_WORK_SLOT_NUM;
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@@ -514,6 +519,7 @@ static void knc_titan_queue_flush(struct thr_info * const thr)
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for (die = 0; die < KNC_TITAN_DIES_PER_ASIC; ++die) {
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knc->dies[asic][die].need_flush = true;
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}
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+ knc->asic_served_by_fpga[asic] = true;
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}
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timer_set_now(&thr->tv_poll);
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}
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@@ -568,6 +574,7 @@ static void knc_titan_poll(struct thr_info * const thr)
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struct knc_titan_die *die_p;
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struct timeval tv_now, tv_prev;
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bool any_was_flushed = false;
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+ int num_request_busy;
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knc_titan_prune_local_queue(thr);
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timer_set_now(&tv_prev);
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@@ -595,7 +602,6 @@ static void knc_titan_poll(struct thr_info * const thr)
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} else {
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/* Use unicasts */
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bool work_acc_arr[die_p->cores];
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- struct knc_report reports[die_p->cores];
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for (proc = first_proc; proc; proc = proc->next_proc) {
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mythr = proc->thr[0];
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core1 = mythr->cgpu_data;
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@@ -603,24 +609,33 @@ static void knc_titan_poll(struct thr_info * const thr)
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break;
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work_acc_arr[core1->coreno] = false;
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}
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- if (knc_titan_set_work_multi(first_proc->device->dev_repr, knc->ctx, asic, die, 0, die_p->next_slot, work, true, work_acc_arr, reports, die_p->cores)) {
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- for (proc = first_proc; proc; proc = proc->next_proc) {
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- mythr = proc->thr[0];
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- core1 = mythr->cgpu_data;
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- if ((core1->dieno != die) || (core1->asicno != asic))
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- break;
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- if (work_acc_arr[core1->coreno]) {
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- /* Submit stale shares just in case we are working with multi-coin pool
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- * and those shares still might be useful (merged mining case etc) */
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- if (knc_titan_process_report(knc, core1, &(reports[core1->coreno])))
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- timer_set_now(&(die_p->last_share));
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- work_accepted = true;
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+ knc_titan_get_work_status(first_proc->device->dev_repr, knc->ctx, asic, &num_request_busy);
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+ if (num_request_busy == 0) {
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+ if (knc_titan_set_work_parallel(first_proc->device->dev_repr, knc->ctx, asic, 1 << die, 0, die_p->next_slot, work, true, work_acc_arr, die_p->cores, KNC_TITAN_FPGA_RETRIES)) {
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+ work_accepted = true;
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+ for (proc = first_proc; proc; proc = proc->next_proc) {
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+ mythr = proc->thr[0];
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+ core1 = mythr->cgpu_data;
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+ if ((core1->dieno != die) || (core1->asicno != asic))
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+ break;
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+ if (work_acc_arr[core1->coreno]) {
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+ /* Submit stale shares just in case we are working with multi-coin pool
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+ * and those shares still might be useful (merged mining case etc) */
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+ /* if (knc_titan_process_report(knc, core1, &(reports[core1->coreno]))) */
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+ /* timer_set_now(&(die_p->last_share)); */
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+ work_accepted = true;
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+ }
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}
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}
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}
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}
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} else {
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- if (!knc_titan_set_work(first_proc->dev_repr, knc->ctx, asic, die, ALL_CORES, die_p->next_slot, work, false, &work_accepted, &report))
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+ if (knc->asic_served_by_fpga[asic]) {
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+ knc_titan_get_work_status(first_proc->device->dev_repr, knc->ctx, asic, &num_request_busy);
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+ if (num_request_busy == 0)
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+ knc->asic_served_by_fpga[asic] = false;
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+ }
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+ if (knc->asic_served_by_fpga[asic] || !knc_titan_set_work(first_proc->dev_repr, knc->ctx, asic, die, ALL_CORES, die_p->next_slot, work, false, &work_accepted, &report))
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work_accepted = false;
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}
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knccore = first_proc->thr[0]->cgpu_data;
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