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@@ -33,6 +33,7 @@ BFG_REGISTER_DRIVER(hashfast_ums_drv)
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#define HASHFAST_HEADER_SIZE 8
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#define HASHFAST_HEADER_SIZE 8
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#define HASHFAST_MAX_DATA 0x3fc
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#define HASHFAST_MAX_DATA 0x3fc
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#define HASHFAST_HASH_SIZE (0x20 + 0xc + 4 + 4 + 2 + 1 + 1)
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#define HASHFAST_HASH_SIZE (0x20 + 0xc + 4 + 4 + 2 + 1 + 1)
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+#define HASHFAST_MAX_VOLTAGES 4
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enum hashfast_opcode {
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enum hashfast_opcode {
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HFOP_NULL = 0,
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HFOP_NULL = 0,
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@@ -84,6 +85,13 @@ float hashfast_temperature_conv(const uint8_t * const data)
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return temp;
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return temp;
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}
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}
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+static inline
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+float hashfast_voltage_conv(const uint8_t vdata)
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+{
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+ // Voltage is 8-bit fraction ranging between 0 V and ~1.2 V
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+ return (float)vdata / 256. * 1.2;
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+}
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+
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struct hashfast_parsed_msg {
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struct hashfast_parsed_msg {
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uint8_t opcode;
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uint8_t opcode;
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uint8_t chipaddr;
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uint8_t chipaddr;
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@@ -267,6 +275,7 @@ struct hashfast_dev_state {
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struct hashfast_chip_state {
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struct hashfast_chip_state {
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struct cgpu_info **coreprocs;
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struct cgpu_info **coreprocs;
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hashfast_isn_t last_isn;
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hashfast_isn_t last_isn;
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+ float voltages[HASHFAST_MAX_VOLTAGES];
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};
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};
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struct hashfast_core_state {
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struct hashfast_core_state {
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@@ -525,6 +534,8 @@ bool hashfast_poll_msg(struct thr_info * const master_thr)
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struct hashfast_chip_state * const chipstate = &devstate->chipstates[msg.chipaddr];
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struct hashfast_chip_state * const chipstate = &devstate->chipstates[msg.chipaddr];
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hashfast_isn_t isn = hashfast_get_isn(chipstate, msg.hdata);
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hashfast_isn_t isn = hashfast_get_isn(chipstate, msg.hdata);
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const float temp = hashfast_temperature_conv(&msg.data[0]);
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const float temp = hashfast_temperature_conv(&msg.data[0]);
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+ for (int i = 0; i < HASHFAST_MAX_VOLTAGES; ++i)
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+ chipstate->voltages[i] = hashfast_voltage_conv(msg.data[2 + i]);
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int cores_uptodate, cores_active, cores_pending, cores_transitioned;
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int cores_uptodate, cores_active, cores_pending, cores_transitioned;
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cores_uptodate = cores_active = cores_pending = cores_transitioned = 0;
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cores_uptodate = cores_active = cores_pending = cores_transitioned = 0;
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for (int i = 0; i < devstate->cores_per_chip; ++i, (proc = proc->next_proc))
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for (int i = 0; i < devstate->cores_per_chip; ++i, (proc = proc->next_proc))
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@@ -589,6 +600,37 @@ void hashfast_poll(struct thr_info * const master_thr)
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timer_set_delay_from_now(&master_thr->tv_poll, 100000);
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timer_set_delay_from_now(&master_thr->tv_poll, 100000);
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}
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}
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+#ifdef HAVE_CURSES
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+static
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+void hashfast_wlogprint_status(struct cgpu_info * const proc)
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+{
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+ struct hashfast_dev_state * const devstate = proc->device_data;
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+ struct thr_info * const thr = proc->thr[0];
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+ struct hashfast_core_state * const cs = thr->cgpu_data;
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+ struct hashfast_chip_state * const chipstate = &devstate->chipstates[cs->chipaddr];
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+
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+ {
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+ // -> "NNN.xxx / NNN.xxx / NNN.xxx"
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+ size_t sz = (HASHFAST_MAX_VOLTAGES * 10) + 1;
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+ char buf[sz];
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+ char *s = buf;
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+ int rv = 0;
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+ for (int i = 0; i < HASHFAST_MAX_VOLTAGES; ++i)
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+ {
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+ const float voltage = chipstate->voltages[i];
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+ if (!voltage)
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+ continue;
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+ _SNP("%.3f / ", voltage);
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+ }
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+ if (rv >= 3 && s[-2] == '/')
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+ {
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+ s[-3] = '\0';
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+ wlogprint("Voltages: %s\n", buf);
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+ }
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+ }
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+}
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+#endif
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+
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struct device_drv hashfast_ums_drv = {
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struct device_drv hashfast_ums_drv = {
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.dname = "hashfast_ums",
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.dname = "hashfast_ums",
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.name = "HFA",
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.name = "HFA",
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@@ -602,4 +644,8 @@ struct device_drv hashfast_ums_drv = {
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.queue_append = hashfast_queue_append,
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.queue_append = hashfast_queue_append,
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.queue_flush = hashfast_queue_flush,
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.queue_flush = hashfast_queue_flush,
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.poll = hashfast_poll,
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.poll = hashfast_poll,
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+
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+#ifdef HAVE_CURSES
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+ .proc_wlogprint_status = hashfast_wlogprint_status,
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+#endif
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};
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};
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