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@@ -0,0 +1,529 @@
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+/*
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+ * Copyright 2012 Luke Dashjr
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the Free
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+ * Software Foundation; either version 3 of the License, or (at your option)
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+ * any later version. See COPYING for more details.
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+ */
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+
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+#include <sys/time.h>
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+
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+#include <libusb-1.0/libusb.h>
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+
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+#include "dynclock.h"
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+#include "jtag.h"
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+#include "logging.h"
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+#include "miner.h"
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+#include "fpgautils.h"
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+#include "ft232r.h"
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+
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+#define X6500_USB_PRODUCT "X6500 FPGA Miner"
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+#define X6500_BITSTREAM_FILENAME "fpgaminer_top_fixed7_197MHz.bit"
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+// NOTE: X6500_BITSTREAM_USERID is bitflipped
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+#define X6500_BITSTREAM_USERID "\x40\x20\x24\x42"
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+#define X6500_MINIMUM_CLOCK 2
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+#define X6500_DEFAULT_CLOCK 190
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+#define X6500_MAXIMUM_CLOCK 250
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+
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+struct device_api x6500_api;
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+
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+#define fromlebytes(ca, j) (ca[j] | (((uint16_t)ca[j+1])<<8) | (((uint32_t)ca[j+2])<<16) | (((uint32_t)ca[j+3])<<24))
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+
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+static
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+void int2bits(uint32_t n, uint8_t *b, uint8_t bits)
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+{
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+ uint8_t i;
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+ for (i = (bits + 7) / 8; i > 0; )
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+ b[--i] = 0;
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+ for (i = 0; i < bits; ++i) {
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+ if (n & 1)
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+ b[i/8] |= 0x80 >> (i % 8);
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+ n >>= 1;
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+ }
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+}
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+
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+static
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+uint32_t bits2int(uint8_t *b, uint8_t bits)
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+{
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+ uint32_t n, i;
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+ n = 0;
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+ for (i = 0; i < bits; ++i)
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+ if (b[i/8] & (0x80 >> (i % 8)))
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+ n |= 1<<i;
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+ return n;
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+}
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+
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+static
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+void checksum(uint8_t *b, uint8_t bits)
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+{
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+ uint8_t i;
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+ uint8_t checksum = 1;
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+ for(i = 0; i < bits; ++i)
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+ checksum ^= (b[i/8] & (0x80 >> (i % 8))) ? 1 : 0;
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+ if (checksum)
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+ b[i/8] |= 0x80 >> (i % 8);
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+}
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+
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+static
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+void x6500_jtag_set(struct jtag_port *jp, uint8_t pinoffset)
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+{
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+ jp->tck = pinoffset << 3;
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+ jp->tms = pinoffset << 2;
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+ jp->tdi = pinoffset << 1;
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+ jp->tdo = pinoffset << 0;
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+ jp->ignored = ~(jp->tdo | jp->tdi | jp->tms | jp->tck);
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+}
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+
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+static uint32_t x6500_get_register(struct jtag_port *jp, uint8_t addr);
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+
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+static
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+void x6500_set_register(struct jtag_port *jp, uint8_t addr, uint32_t nv)
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+{
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+ uint8_t buf[38];
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+retry:
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+ jtag_write(jp, JTAG_REG_IR, "\x40", 6);
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+ int2bits(nv, &buf[0], 32);
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+ int2bits(addr, &buf[4], 4);
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+ buf[4] |= 8;
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+ checksum(buf, 37);
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+ jtag_write(jp, JTAG_REG_DR, buf, 38);
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+ jtag_run(jp);
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+#ifdef DEBUG_X6500_SET_REGISTER
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+ if (x6500_get_register(jp, addr) != nv)
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+#else
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+ if (0)
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+#endif
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+ {
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+ applog(LOG_WARNING, "x6500_set_register failed %x=%08x", addr, nv);
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+ goto retry;
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+ }
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+}
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+
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+static
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+uint32_t x6500_get_register(struct jtag_port *jp, uint8_t addr)
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+{
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+ uint8_t buf[4];
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+ jtag_write(jp, JTAG_REG_IR, "\x40", 6);
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+ int2bits(addr, &buf[0], 4);
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+ checksum(buf, 5);
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+ jtag_write(jp, JTAG_REG_DR, buf, 6);
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+ jtag_read (jp, JTAG_REG_DR, buf, 32);
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+ jtag_reset(jp);
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+ return bits2int(buf, 32);
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+}
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+
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+static bool x6500_foundusb(libusb_device *dev, const char *product, const char *serial)
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+{
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+ struct cgpu_info *x6500;
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+ x6500 = calloc(1, sizeof(*x6500));
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+ x6500->api = &x6500_api;
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+ mutex_init(&x6500->device_mutex);
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+ x6500->device_path = strdup(serial);
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+ x6500->deven = DEV_ENABLED;
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+ x6500->threads = 2;
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+ x6500->name = strdup(product);
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+ x6500->cutofftemp = 85;
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+ x6500->cgpu_data = dev;
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+
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+ return add_cgpu(x6500);
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+}
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+
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+static bool x6500_detect_one(const char *serial)
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+{
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+ return ft232r_detect(X6500_USB_PRODUCT, serial, x6500_foundusb);
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+}
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+
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+static int x6500_detect_auto()
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+{
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+ return ft232r_detect(X6500_USB_PRODUCT, NULL, x6500_foundusb);
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+}
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+
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+static void x6500_detect()
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+{
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+ serial_detect_auto(&x6500_api, x6500_detect_one, x6500_detect_auto);
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+}
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+
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+static bool x6500_prepare(struct thr_info *thr)
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+{
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+ if (thr->device_thread)
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+ return true;
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+
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+ struct cgpu_info *x6500 = thr->cgpu;
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+ mutex_init(&x6500->device_mutex);
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+ struct ft232r_device_handle *ftdi = ft232r_open(x6500->cgpu_data);
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+ x6500->device_ft232r = NULL;
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+ if (!ftdi)
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+ return false;
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+ if (!ft232r_set_bitmode(ftdi, 0xee, 4))
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+ return false;
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+ if (!ft232r_purge_buffers(ftdi, FTDI_PURGE_BOTH))
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+ return false;
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+ x6500->device_ft232r = ftdi;
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+
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+ struct jtag_port_a *jtag_a;
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+ unsigned char *pdone = calloc(1, sizeof(*jtag_a) + 1);
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+ *pdone = 101;
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+ jtag_a = (void*)(pdone + 1);
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+ jtag_a->ftdi = ftdi;
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+ x6500->cgpu_data = jtag_a;
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+
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+ return true;
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+}
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+
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+struct x6500_fpga_data {
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+ struct jtag_port jtag;
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+ struct work prevwork;
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+ struct timeval tv_workstart;
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+
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+ struct dclk_data dclk;
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+};
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+
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+#define bailout2(...) do { \
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+ applog(__VA_ARGS__); \
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+ return false; \
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+} while(0)
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+
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+static bool
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+x6500_fpga_upload_bitstream(struct cgpu_info *x6500, struct jtag_port *jp1)
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+{
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+ char buf[0x100];
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+ unsigned long len, flen;
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+ unsigned char *pdone = (unsigned char*)x6500->cgpu_data - 1;
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+ struct ft232r_device_handle *ftdi = jp1->a->ftdi;
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+
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+ FILE *f = open_xilinx_bitstream(x6500, X6500_BITSTREAM_FILENAME, &len);
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+ if (!f)
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+ return false;
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+
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+ flen = len;
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+
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+ applog(LOG_WARNING, "%s %u: Programming %s...",
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+ x6500->api->name, x6500->device_id, x6500->device_path);
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+
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+ // "Magic" jtag_port configured to access both FPGAs concurrently
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+ struct jtag_port jpt = {
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+ .a = jp1->a,
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+ };
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+ struct jtag_port *jp = &jpt;
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+ uint8_t i, j;
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+ x6500_jtag_set(jp, 0x11);
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+
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+ // Need to reset here despite previous FPGA state, since we are programming all at once
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+ jtag_reset(jp);
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+
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+ jtag_write(jp, JTAG_REG_IR, "\xd0", 6); // JPROGRAM
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+ // Poll each FPGA status individually since they might not be ready at the same time
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+ for (j = 0; j < 2; ++j) {
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+ x6500_jtag_set(jp, j ? 0x10 : 1);
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+ do {
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+ i = 0xd0; // Re-set JPROGRAM while reading status
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+ jtag_read(jp, JTAG_REG_IR, &i, 6);
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+ } while (i & 8);
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+ applog(LOG_DEBUG, "%s %u.%u: JPROGRAM ready",
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+ x6500->api->name, x6500->device_id, j);
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+ }
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+ x6500_jtag_set(jp, 0x11);
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+ jtag_write(jp, JTAG_REG_IR, "\xa0", 6); // CFG_IN
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+
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+ sleep(1);
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+
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+ if (fread(buf, 32, 1, f) != 1)
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+ bailout2(LOG_ERR, "%s %u: File underrun programming %s (%d bytes left)", x6500->api->name, x6500->device_id, x6500->device_path, len);
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+ jtag_swrite(jp, JTAG_REG_DR, buf, 256);
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+ len -= 32;
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+
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+ // Put ft232r chip in asynchronous bitbang mode so we don't need to read back tdo
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+ // This takes upload time down from about an hour to about 3 minutes
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+ if (!ft232r_set_bitmode(ftdi, 0xee, 1))
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+ return false;
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+ if (!ft232r_purge_buffers(ftdi, FTDI_PURGE_BOTH))
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+ return false;
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+ jp->a->async = true;
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+
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+ ssize_t buflen;
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+ char nextstatus = 25;
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+ while (len) {
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+ buflen = len < 32 ? len : 32;
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+ if (fread(buf, buflen, 1, f) != 1)
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+ bailout2(LOG_ERR, "%s %u: File underrun programming %s (%d bytes left)", x6500->api->name, x6500->device_id, x6500->device_path, len);
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+ jtag_swrite_more(jp, buf, buflen * 8, len == (unsigned long)buflen);
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+ *pdone = 100 - ((len * 100) / flen);
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+ if (*pdone >= nextstatus)
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+ {
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+ nextstatus += 25;
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+ applog(LOG_WARNING, "%s %u: Programming %s... %d%% complete...", x6500->api->name, x6500->device_id, x6500->device_path, *pdone);
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+ }
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+ len -= buflen;
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+ }
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+
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+ // Switch back to synchronous bitbang mode
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+ if (!ft232r_set_bitmode(ftdi, 0xee, 4))
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+ return false;
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+ if (!ft232r_purge_buffers(ftdi, FTDI_PURGE_BOTH))
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+ return false;
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+ jp->a->async = false;
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+ jp->a->bufread = 0;
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+
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+ jtag_write(jp, JTAG_REG_IR, "\x30", 6); // JSTART
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+ for (i=0; i<16; ++i)
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+ jtag_run(jp);
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+ i = 0xff; // BYPASS
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+ jtag_read(jp, JTAG_REG_IR, &i, 6);
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+ if (!(i & 4))
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+ return false;
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+
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+ applog(LOG_WARNING, "%s %u: Done programming %s", x6500->api->name, x6500->device_id, x6500->device_path);
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+ *pdone = 101;
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+
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+ return true;
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+}
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+
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+static bool x6500_change_clock(struct thr_info *thr, int multiplier)
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+{
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+ struct x6500_fpga_data *fpga = thr->cgpu_data;
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+ struct jtag_port *jp = &fpga->jtag;
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+
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+ x6500_set_register(jp, 0xD, multiplier * 2);
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+ ft232r_flush(jp->a->ftdi);
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+ fpga->dclk.freqM = multiplier;
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+
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+ return true;
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+}
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+
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+static bool x6500_dclk_change_clock(struct thr_info *thr, int multiplier)
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+{
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|
|
|
|
+ struct cgpu_info *x6500 = thr->cgpu;
|
|
|
|
|
+ char fpgaid = thr->device_thread;
|
|
|
|
|
+ struct x6500_fpga_data *fpga = thr->cgpu_data;
|
|
|
|
|
+ uint8_t oldFreq = fpga->dclk.freqM;
|
|
|
|
|
+
|
|
|
|
|
+ mutex_lock(&x6500->device_mutex);
|
|
|
|
|
+ if (!x6500_change_clock(thr, multiplier)) {
|
|
|
|
|
+ mutex_unlock(&x6500->device_mutex);
|
|
|
|
|
+ return false;
|
|
|
|
|
+ }
|
|
|
|
|
+ mutex_unlock(&x6500->device_mutex);
|
|
|
|
|
+
|
|
|
|
|
+ char repr[0x10];
|
|
|
|
|
+ sprintf(repr, "%s %u.%u", x6500->api->name, x6500->device_id, fpgaid);
|
|
|
|
|
+ dclk_msg_freqchange(repr, oldFreq * 2, fpga->dclk.freqM * 2, NULL);
|
|
|
|
|
+ return true;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static bool x6500_fpga_init(struct thr_info *thr)
|
|
|
|
|
+{
|
|
|
|
|
+ struct cgpu_info *x6500 = thr->cgpu;
|
|
|
|
|
+ struct ft232r_device_handle *ftdi = x6500->device_ft232r;
|
|
|
|
|
+ struct x6500_fpga_data *fpga;
|
|
|
|
|
+ struct jtag_port *jp;
|
|
|
|
|
+ int fpgaid = thr->device_thread;
|
|
|
|
|
+ uint8_t pinoffset = fpgaid ? 0x10 : 1;
|
|
|
|
|
+ unsigned char buf[4];
|
|
|
|
|
+ int i;
|
|
|
|
|
+
|
|
|
|
|
+ if (!ftdi)
|
|
|
|
|
+ return false;
|
|
|
|
|
+
|
|
|
|
|
+ thread_reportin(thr); // HACK
|
|
|
|
|
+
|
|
|
|
|
+ fpga = calloc(1, sizeof(*fpga));
|
|
|
|
|
+ jp = &fpga->jtag;
|
|
|
|
|
+ jp->a = x6500->cgpu_data;
|
|
|
|
|
+ x6500_jtag_set(jp, pinoffset);
|
|
|
|
|
+
|
|
|
|
|
+ mutex_lock(&x6500->device_mutex);
|
|
|
|
|
+ if (!jtag_reset(jp)) {
|
|
|
|
|
+ mutex_unlock(&x6500->device_mutex);
|
|
|
|
|
+ applog(LOG_ERR, "%s %u: JTAG reset failed",
|
|
|
|
|
+ x6500->api->name, x6500->device_id);
|
|
|
|
|
+ return false;
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ i = jtag_detect(jp);
|
|
|
|
|
+ if (i != 1) {
|
|
|
|
|
+ mutex_unlock(&x6500->device_mutex);
|
|
|
|
|
+ applog(LOG_ERR, "%s %u: JTAG detect returned %d",
|
|
|
|
|
+ x6500->api->name, x6500->device_id, i);
|
|
|
|
|
+ return false;
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ if (!(1
|
|
|
|
|
+ && jtag_write(jp, JTAG_REG_IR, "\x10", 6)
|
|
|
|
|
+ && jtag_read (jp, JTAG_REG_DR, buf, 32)
|
|
|
|
|
+ && jtag_reset(jp)
|
|
|
|
|
+ )) {
|
|
|
|
|
+ mutex_unlock(&x6500->device_mutex);
|
|
|
|
|
+ applog(LOG_ERR, "%s %u: JTAG error reading user code",
|
|
|
|
|
+ x6500->api->name, x6500->device_id);
|
|
|
|
|
+ return false;
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ if (memcmp(buf, X6500_BITSTREAM_USERID, 4)) {
|
|
|
|
|
+ applog(LOG_ERR, "%s %u.%u: FPGA not programmed",
|
|
|
|
|
+ x6500->api->name, x6500->device_id, fpgaid);
|
|
|
|
|
+ if (!x6500_fpga_upload_bitstream(x6500, jp))
|
|
|
|
|
+ return false;
|
|
|
|
|
+ } else
|
|
|
|
|
+ applog(LOG_DEBUG, "%s %u.%u: FPGA is already programmed :)",
|
|
|
|
|
+ x6500->api->name, x6500->device_id, fpgaid);
|
|
|
|
|
+
|
|
|
|
|
+ thr->cgpu_data = fpga;
|
|
|
|
|
+
|
|
|
|
|
+ dclk_prepare(&fpga->dclk);
|
|
|
|
|
+ fpga->dclk.freqMaxM = X6500_MAXIMUM_CLOCK / 2;
|
|
|
|
|
+ x6500_change_clock(thr, X6500_DEFAULT_CLOCK / 2);
|
|
|
|
|
+ fpga->dclk.freqMDefault = fpga->dclk.freqM;
|
|
|
|
|
+ applog(LOG_WARNING, "%s %u.%u: Frequency set to %u Mhz (range: %u-%u)",
|
|
|
|
|
+ x6500->api->name, x6500->device_id, fpgaid,
|
|
|
|
|
+ fpga->dclk.freqM * 2,
|
|
|
|
|
+ X6500_MINIMUM_CLOCK,
|
|
|
|
|
+ fpga->dclk.freqMaxM * 2);
|
|
|
|
|
+
|
|
|
|
|
+ mutex_unlock(&x6500->device_mutex);
|
|
|
|
|
+ return true;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static void
|
|
|
|
|
+get_x6500_statline_before(char *buf, struct cgpu_info *x6500)
|
|
|
|
|
+{
|
|
|
|
|
+ char info[18] = " | ";
|
|
|
|
|
+
|
|
|
|
|
+ unsigned char pdone = *((unsigned char*)x6500->cgpu_data - 1);
|
|
|
|
|
+ if (pdone != 101) {
|
|
|
|
|
+ sprintf(&info[1], "%3d%%", pdone);
|
|
|
|
|
+ info[5] = ' ';
|
|
|
|
|
+ strcat(buf, info);
|
|
|
|
|
+ return;
|
|
|
|
|
+ }
|
|
|
|
|
+ strcat(buf, " | ");
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static
|
|
|
|
|
+bool x6500_start_work(struct thr_info *thr, struct work *work)
|
|
|
|
|
+{
|
|
|
|
|
+ struct cgpu_info *x6500 = thr->cgpu;
|
|
|
|
|
+ struct x6500_fpga_data *fpga = thr->cgpu_data;
|
|
|
|
|
+ struct jtag_port *jp = &fpga->jtag;
|
|
|
|
|
+ char fpgaid = thr->device_thread;
|
|
|
|
|
+
|
|
|
|
|
+ mutex_lock(&x6500->device_mutex);
|
|
|
|
|
+
|
|
|
|
|
+ for (int i = 1, j = 0; i < 9; ++i, j += 4)
|
|
|
|
|
+ x6500_set_register(jp, i, fromlebytes(work->midstate, j));
|
|
|
|
|
+
|
|
|
|
|
+ for (int i = 9, j = 64; i < 12; ++i, j += 4)
|
|
|
|
|
+ x6500_set_register(jp, i, fromlebytes(work->data, j));
|
|
|
|
|
+
|
|
|
|
|
+ ft232r_flush(jp->a->ftdi);
|
|
|
|
|
+
|
|
|
|
|
+ gettimeofday(&fpga->tv_workstart, NULL);
|
|
|
|
|
+ mutex_unlock(&x6500->device_mutex);
|
|
|
|
|
+
|
|
|
|
|
+ if (opt_debug) {
|
|
|
|
|
+ char *xdata = bin2hex(work->data, 80);
|
|
|
|
|
+ applog(LOG_DEBUG, "%s %u.%u: Started work: %s",
|
|
|
|
|
+ x6500->api->name, x6500->device_id, fpgaid, xdata);
|
|
|
|
|
+ free(xdata);
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ return true;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static
|
|
|
|
|
+int64_t calc_hashes(struct x6500_fpga_data *fpga, struct timeval *tv_now)
|
|
|
|
|
+{
|
|
|
|
|
+ struct timeval tv_delta;
|
|
|
|
|
+ int64_t hashes;
|
|
|
|
|
+
|
|
|
|
|
+ timersub(tv_now, &fpga->tv_workstart, &tv_delta);
|
|
|
|
|
+ hashes = (((int64_t)tv_delta.tv_sec * 1000000) + tv_delta.tv_usec) * fpga->dclk.freqM * 2;
|
|
|
|
|
+ if (unlikely(hashes > 0x100000000))
|
|
|
|
|
+ hashes = 0x100000000;
|
|
|
|
|
+ return hashes;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static
|
|
|
|
|
+int64_t x6500_process_results(struct thr_info *thr, struct work *work)
|
|
|
|
|
+{
|
|
|
|
|
+ struct cgpu_info *x6500 = thr->cgpu;
|
|
|
|
|
+ struct x6500_fpga_data *fpga = thr->cgpu_data;
|
|
|
|
|
+ struct jtag_port *jtag = &fpga->jtag;
|
|
|
|
|
+ char fpgaid = thr->device_thread;
|
|
|
|
|
+
|
|
|
|
|
+ struct timeval tv_now;
|
|
|
|
|
+ int64_t hashes;
|
|
|
|
|
+ uint32_t nonce;
|
|
|
|
|
+ bool bad;
|
|
|
|
|
+ int imm_bad_nonces = 0, imm_nonces = 0;
|
|
|
|
|
+
|
|
|
|
|
+ while (1) {
|
|
|
|
|
+ mutex_lock(&x6500->device_mutex);
|
|
|
|
|
+ gettimeofday(&tv_now, NULL);
|
|
|
|
|
+ nonce = x6500_get_register(jtag, 0xE);
|
|
|
|
|
+ mutex_unlock(&x6500->device_mutex);
|
|
|
|
|
+ if (nonce != 0xffffffff) {
|
|
|
|
|
+ ++imm_nonces;
|
|
|
|
|
+ bad = !test_nonce(work, nonce, false);
|
|
|
|
|
+ if (!bad) {
|
|
|
|
|
+ submit_nonce(thr, work, nonce);
|
|
|
|
|
+ applog(LOG_DEBUG, "%s %u.%u: Nonce for current work: %08lx",
|
|
|
|
|
+ x6500->api->name, x6500->device_id, fpgaid,
|
|
|
|
|
+ (unsigned long)nonce);
|
|
|
|
|
+ } else if (test_nonce(&fpga->prevwork, nonce, false)) {
|
|
|
|
|
+ submit_nonce(thr, &fpga->prevwork, nonce);
|
|
|
|
|
+ applog(LOG_DEBUG, "%s %u.%u: Nonce for PREVIOUS work: %08lx",
|
|
|
|
|
+ x6500->api->name, x6500->device_id, fpgaid,
|
|
|
|
|
+ (unsigned long)nonce);
|
|
|
|
|
+ } else {
|
|
|
|
|
+ applog(LOG_DEBUG, "%s %u.%u: Nonce with H not zero : %08lx",
|
|
|
|
|
+ x6500->api->name, x6500->device_id, fpgaid,
|
|
|
|
|
+ (unsigned long)nonce);
|
|
|
|
|
+ ++hw_errors;
|
|
|
|
|
+ ++x6500->hw_errors;
|
|
|
|
|
+ ++imm_bad_nonces;
|
|
|
|
|
+ }
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ hashes = calc_hashes(fpga, &tv_now);
|
|
|
|
|
+ if (thr->work_restart || hashes >= 0xf0000000)
|
|
|
|
|
+ break;
|
|
|
|
|
+ usleep(10000);
|
|
|
|
|
+ hashes = calc_hashes(fpga, &tv_now);
|
|
|
|
|
+ if (thr->work_restart || hashes >= 0xf0000000)
|
|
|
|
|
+ break;
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ dclk_gotNonces(&fpga->dclk);
|
|
|
|
|
+ if (imm_bad_nonces)
|
|
|
|
|
+ dclk_errorCount(&fpga->dclk, ((double)imm_bad_nonces) / (double)imm_nonces);
|
|
|
|
|
+ dclk_preUpdate(&fpga->dclk);
|
|
|
|
|
+ dclk_updateFreq(&fpga->dclk, x6500_dclk_change_clock, thr);
|
|
|
|
|
+
|
|
|
|
|
+ memcpy(&fpga->prevwork, work, sizeof(fpga->prevwork));
|
|
|
|
|
+
|
|
|
|
|
+ return hashes;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static int64_t
|
|
|
|
|
+x6500_scanhash(struct thr_info *thr, struct work *work, int64_t __maybe_unused max_nonce)
|
|
|
|
|
+{
|
|
|
|
|
+ if (!x6500_start_work(thr, work))
|
|
|
|
|
+ return -1;
|
|
|
|
|
+
|
|
|
|
|
+ int64_t hashes = x6500_process_results(thr, work);
|
|
|
|
|
+ if (hashes > 0)
|
|
|
|
|
+ work->blk.nonce += hashes;
|
|
|
|
|
+ return hashes;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+struct device_api x6500_api = {
|
|
|
|
|
+ .dname = "x6500",
|
|
|
|
|
+ .name = "XBS",
|
|
|
|
|
+ .api_detect = x6500_detect,
|
|
|
|
|
+ .thread_prepare = x6500_prepare,
|
|
|
|
|
+ .thread_init = x6500_fpga_init,
|
|
|
|
|
+ .get_statline_before = get_x6500_statline_before,
|
|
|
|
|
+ .scanhash = x6500_scanhash,
|
|
|
|
|
+// .thread_shutdown = x6500_fpga_shutdown,
|
|
|
|
|
+};
|