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@@ -309,7 +309,7 @@ bool aan_init(struct thr_info * const master_thr)
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*chip = (struct aan_chip_data){
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*chip = (struct aan_chip_data){
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.chipid = ++chipid,
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.chipid = ++chipid,
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.desired_nonce_pdiff = AAN_DEFAULT_NONCE_PDIFF,
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.desired_nonce_pdiff = AAN_DEFAULT_NONCE_PDIFF,
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- .pllreg = 0x87a9, // 850 MHz
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+ .desired_pllreg = 0x87a9, // 850 MHz
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};
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};
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}
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}
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master_thr->tv_poll = tv_now;
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master_thr->tv_poll = tv_now;
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@@ -529,15 +529,16 @@ badjob:
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continue;
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continue;
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}
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}
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const uint16_t pllreg = upk_u16be(reg, 0);
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const uint16_t pllreg = upk_u16be(reg, 0);
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- if (pllreg != chip->pllreg)
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+ chip->current_pllreg = pllreg;
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+ if (pllreg != chip->desired_pllreg)
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{
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{
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// Wait for chip to idle before changing register
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// Wait for chip to idle before changing register
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if (!(reg[3] & 3))
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if (!(reg[3] & 3))
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{
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{
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- applog(LOG_DEBUG, "%"PRIpreprv": Asserting PLL change: %04x->%04x", proc->proc_repr, pllreg, chip->pllreg);
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+ applog(LOG_DEBUG, "%"PRIpreprv": Asserting PLL change: %04x->%04x", proc->proc_repr, pllreg, chip->desired_pllreg);
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uint8_t regset[AAN_REGISTER_SIZE];
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uint8_t regset[AAN_REGISTER_SIZE];
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memcpy(®set[2], ®[2], AAN_REGISTER_SIZE - 2);
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memcpy(®set[2], ®[2], AAN_REGISTER_SIZE - 2);
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- pk_u16be(regset, 0, chip->pllreg);
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+ pk_u16be(regset, 0, chip->desired_pllreg);
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aan_spi_cmd_send(spi, AAN_WRITE_REG, chip->chipid, regset, AAN_REGISTER_SIZE);
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aan_spi_cmd_send(spi, AAN_WRITE_REG, chip->chipid, regset, AAN_REGISTER_SIZE);
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}
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}
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}
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}
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@@ -591,7 +592,7 @@ const char *aan_set_clock(struct cgpu_info * const proc, const char * const optn
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if (nv <= 0 || nv > AAN_MAX_FREQ)
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if (nv <= 0 || nv > AAN_MAX_FREQ)
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return "Invalid clock frequency";
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return "Invalid clock frequency";
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- chip->pllreg = aan_freq2pll(nv);
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+ chip->desired_pllreg = aan_freq2pll(nv);
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return NULL;
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return NULL;
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}
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}
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@@ -610,6 +611,18 @@ const char *aan_set_diff(struct cgpu_info * const proc, const char * const optna
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return NULL;
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return NULL;
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}
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}
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+struct api_data *aan_api_device_status(struct cgpu_info * const proc)
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+{
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+ struct thr_info * const thr = proc->thr[0];
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+ struct aan_chip_data * const chip = thr->cgpu_data;
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+ struct api_data *root = NULL;
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+
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+ double mhz = aan_pll2freq(chip->current_pllreg);
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+ root = api_add_freq(root, "Frequency", &mhz, true);
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+
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+ return root;
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+}
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+
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const struct bfg_set_device_definition aan_set_device_funcs[] = {
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const struct bfg_set_device_definition aan_set_device_funcs[] = {
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{"clock", aan_set_clock, "clock frequency (MHz)"},
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{"clock", aan_set_clock, "clock frequency (MHz)"},
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{"diff", aan_set_diff, "desired nonce difficulty"},
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{"diff", aan_set_diff, "desired nonce difficulty"},
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