Browse Source

Merge commit 'd198bdf' into bfgminer

Luke Dashjr 12 years ago
parent
commit
0e9bd81413
6 changed files with 8 additions and 2 deletions
  1. 1 0
      driver-cairnsmore.c
  2. 1 0
      driver-modminer.c
  3. 1 0
      driver-x6500.c
  4. 3 2
      dynclock.c
  5. 1 0
      dynclock.h
  6. 1 0
      libztex.c

+ 1 - 0
driver-cairnsmore.c

@@ -133,6 +133,7 @@ static bool cairnsmore_init(struct thr_info *thr)
 		info->dclk_change_clock_func = cairnsmore_change_clock_func;
 		info->dclk_change_clock_func = cairnsmore_change_clock_func;
 
 
 		dclk_prepare(&info->dclk);
 		dclk_prepare(&info->dclk);
+		info->dclk.freqMinM = CAIRNSMORE1_MINIMUM_CLOCK / 2.5;
 		info->dclk.freqMaxM = CAIRNSMORE1_MAXIMUM_CLOCK / 2.5;
 		info->dclk.freqMaxM = CAIRNSMORE1_MAXIMUM_CLOCK / 2.5;
 		info->dclk.freqM =
 		info->dclk.freqM =
 		info->dclk.freqMDefault = CAIRNSMORE1_DEFAULT_CLOCK / 2.5;
 		info->dclk.freqMDefault = CAIRNSMORE1_DEFAULT_CLOCK / 2.5;

+ 1 - 0
driver-modminer.c

@@ -294,6 +294,7 @@ modminer_fpga_prepare(struct thr_info *thr)
 	struct modminer_fpga_state *state;
 	struct modminer_fpga_state *state;
 	state = thr->cgpu_data = calloc(1, sizeof(struct modminer_fpga_state));
 	state = thr->cgpu_data = calloc(1, sizeof(struct modminer_fpga_state));
 	dclk_prepare(&state->dclk);
 	dclk_prepare(&state->dclk);
+	state->dclk.freqMinM = MODMINER_MIN_CLOCK / 2;
 	state->next_work_cmd[0] = MODMINER_SEND_WORK;
 	state->next_work_cmd[0] = MODMINER_SEND_WORK;
 	state->next_work_cmd[1] = proc->proc_id;  // FPGA id
 	state->next_work_cmd[1] = proc->proc_id;  // FPGA id
 	
 	

+ 1 - 0
driver-x6500.c

@@ -405,6 +405,7 @@ static bool x6500_thread_init(struct thr_info *thr)
 		       x6500->proc_repr);
 		       x6500->proc_repr);
 	
 	
 	dclk_prepare(&fpga->dclk);
 	dclk_prepare(&fpga->dclk);
+	fpga->dclk.freqMinM = X6500_MINIMUM_CLOCK / 2;
 	x6500_change_clock(thr, X6500_DEFAULT_CLOCK / 2);
 	x6500_change_clock(thr, X6500_DEFAULT_CLOCK / 2);
 	for (i = 0; 0xffffffff != x6500_get_register(jp, 0xE); ++i)
 	for (i = 0; 0xffffffff != x6500_get_register(jp, 0xE); ++i)
 	{}
 	{}

+ 3 - 2
dynclock.c

@@ -17,6 +17,7 @@ void dclk_prepare(struct dclk_data *data)
 {
 {
 	*data = (struct dclk_data){
 	*data = (struct dclk_data){
 		.minGoodSamples = 150.,
 		.minGoodSamples = 150.,
+		.freqMinM = 1,
 	};
 	};
 }
 }
 
 
@@ -52,9 +53,9 @@ bool dclk_updateFreq(struct dclk_data *data, dclk_change_clock_func_t changecloc
 	while (maxM < data->freqMaxM && data->maxErrorRate[maxM + 1] < DCLK_MAXMAXERRORRATE && data->errorWeight[maxM] >= data->minGoodSamples)
 	while (maxM < data->freqMaxM && data->maxErrorRate[maxM + 1] < DCLK_MAXMAXERRORRATE && data->errorWeight[maxM] >= data->minGoodSamples)
 		maxM++;
 		maxM++;
 
 
-	bestM = 0;
+	bestM = data->freqMinM;
 	bestR = 0;
 	bestR = 0;
-	for (i = 0; i <= maxM; i++) {
+	for (i = bestM; i <= maxM; i++) {
 		r = (i + 1 + (i == data->freqM? DCLK_ERRORHYSTERESIS: 0)) * (1 - data->maxErrorRate[i]);
 		r = (i + 1 + (i == data->freqM? DCLK_ERRORHYSTERESIS: 0)) * (1 - data->maxErrorRate[i]);
 		if (r > bestR) {
 		if (r > bestR) {
 			bestM = i;
 			bestM = i;

+ 1 - 0
dynclock.h

@@ -22,6 +22,7 @@ struct thr_info;
 
 
 struct dclk_data {
 struct dclk_data {
 	uint8_t freqM;
 	uint8_t freqM;
+	uint8_t freqMinM;
 	uint8_t freqMaxM;
 	uint8_t freqMaxM;
 	uint8_t freqMDefault;
 	uint8_t freqMDefault;
 
 

+ 1 - 0
libztex.c

@@ -582,6 +582,7 @@ int libztex_prepare_device(struct libusb_device *dev, struct libztex_device** zt
 	unsigned char buf[64];
 	unsigned char buf[64];
 
 
 	dclk_prepare(&newdev->dclk);
 	dclk_prepare(&newdev->dclk);
+	newdev->dclk.freqMinM = 0;
 	err = libusb_open(dev, &newdev->hndl);
 	err = libusb_open(dev, &newdev->hndl);
 	if (err != LIBUSB_SUCCESS) {
 	if (err != LIBUSB_SUCCESS) {
 		applog(LOG_ERR, "%s: Can not open ZTEX device: %s", __func__, bfg_strerror(err, BST_LIBUSB));
 		applog(LOG_ERR, "%s: Can not open ZTEX device: %s", __func__, bfg_strerror(err, BST_LIBUSB));